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| RF1K49211 Data Sheet January 2002 7A, 12V, 0.020 Ohm, Logic Level, Single N-Channel LittleFETTM Power MOSFET The RF1K49211 Single N-Channel power MOSFET is manufactured using an advanced MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. It was designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers, and low-voltage bus switches. This product achieves full-rated conduction at a gate bias in the 3V - 5V range, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. Formerly developmental type TA49211. Features * 7A, 12V * rDS(ON) = 0.020 * Temperature Compensating PSPICE(R) Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol NC(1) DRAIN(8) Ordering Information PART NUMBER RF1K49211 PACKAGE MS-012AA BRAND RF1K49211 SOURCE(2) DRAIN(7) NOTE: When ordering, use the entire part number. For ordering in tape and reel, add the suffix 96 to the part number, i.e., RF1K4921196. SOURCE(3) DRAIN(6) GATE(4) DRAIN(5) Packaging JEDEC MS-012AA BRANDING DASH 5 1 2 3 4 (c)2002 Fairchild Semiconductor Corporation RF1K49211 Rev. B RF1K49211 Absolute Maximum Ratings TA = 25oC Unless Otherwise Specified RF1K49211 Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (Rgs = 20K) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Pulse Width = 1s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 12 12 10 7 Refer to Peak Current Curve Refer to UIS Curve 2 0.016 -55 to 150 300 260 W W/oC oC oC oC UNITS V V V A CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TA = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V, (Figure 13) VGS = VDS, ID = 250A, (Figure 12) VDS = 12V, VGS = 0V VGS = 10V ID = 7A, VGS = 5V, (Figures 9, 11) VDD = 6V, ID 7A, RL = 0.86, V GS = 5V, RGS = 25 TA = 25oC TA = 150oC MIN 12 1 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 9.6V, ID 7A, RL = 1.37 Ig(REF) = 1.0mA (Figure15) Pulse Width = 1s Device mounted on FR-4 material TYP 50 150 120 160 60 35 2 1850 1600 600 MAX 2 1 50 100 0.020 250 350 75 45 2.5 62.5 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF oC/W Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Ambient IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RJA VDS = 12V, VGS = 0V, f = 1MHz (Figure 14) Source to Drain Diode Specifications PARAMETERS Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr ISD = 7A ISD = 7A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 95 UNITS V ns (c)2002 Fairchild Semiconductor Corporation RF1K49211 Rev. B RF1K49211 Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 6 0.8 8 0.6 0.4 4 2 0.2 0 0 25 50 75 100 125 TA , AMBIENT TEMPERATURE (oC) 150 0 25 75 100 125 50 TA, AMBIENT TEMPERATURE (oC) 150 FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE 10 ZJA, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 0.01 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-3 10-2 10-1 100 101 102 103 SINGLE PULSE 0.001 10-5 10-4 t1 , RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 100 TJ = MAX RATED TA = 25oC IDM, PEAK CURRENT (A) 300 ID, DRAIN CURRENT (A) 10 5ms 10ms 1 100ms 1s 0.1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.01 0.1 1 DC VDSS(MAX) = 12V 10 50 100 VGS = 5V TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TA 125 10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 1 10-5 10-4 10-3 10-2 10-1 100 101 VDS, DRAIN TO SOURCE VOLTAGE (V) t, PULSE WIDTH (s) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY (c)2002 Fairchild Semiconductor Corporation RF1K49211 Rev. B RF1K49211 Typical Performance Curves 50 IAS, AVALANCHE CURRENT (A) (Continued) 50 VGS = 10V ID, DRAIN CURRENT (A) 40 VGS = 5V VGS = 4V 30 VGS = 3V 20 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC STARTING TJ = 25oC 10 STARTING TJ = 150oC 1 0.01 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100 10 VGS = 2.5V 0 0 1 2 3 4 5 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS 50 ID(ON), ON-STATE DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 40 25oC -55oC rDS(ON), ON-STATE RESISTANCE (m) VDD = 10V 200 ID = 15A ID = 7.0A ID = 3.5A ID = 1.75A PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 10V 150oC 150 30 100 20 50 10 0 0 1 2 3 4 VGS, GATE TO SOURCE VOLTAGE (V) 5 0 2 2.5 3 3.5 4 4.5 5 VGS , GATE TO SOURCE VOLTAGE (V) FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 350 300 SWITCHING TIME (ns) 250 200 150 100 50 0 VDD = 6V, ID = 7A, RL= 0.86 2.0 NORMALIZED ON RESISTANCE tf tr PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 5V, ID = 7A 1.5 td(OFF) 1.0 td(ON) 0.5 0 10 20 30 40 50 0.0 -80 -40 0 40 80 120 160 RGS, GATE TO SOURCE RESISTANCE () TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. SWITCHING TIME vs GATE TO SOURCE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE (c)2002 Fairchild Semiconductor Corporation RF1K49211 Rev. B RF1K49211 Typical Performance Curves 1.2 VGS = VDS, ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE (Continued) 1.2 ID = 250A THRESHOLD VOLTAGE NORMALIZED GATE 1.1 1.0 1.0 0.8 0.9 0.6 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 0.8 -80 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 160 FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 3500 3000 C, CAPACITANCE (pF) 2500 CISS 2000 1500 1000 500 0 CRSS COSS FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 12 VDD = BVDSS 9 RL = 1.71 IG(REF) = 0.75mA VGS = 5V PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS VDD = BVDSS 3.75 5.00 VGS , GATE TO SOURCE VOLTAGE (V) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD VDS , DRAIN TO SOURCE VOLTAGE (V) 6 2.50 3 1.25 0 0 I G ( REF ) 0 2 4 6 8 10 12 VDS , DRAIN TO SOURCE VOLTAGE (V) 20 --------------------I G ( ACT ) I G ( REF ) t, TIME (s) 80 --------------------I G ( ACT ) NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01 0 tAV FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS (c)2002 Fairchild Semiconductor Corporation RF1K49211 Rev. B RF1K49211 Test Circuits and Waveforms VDS (Continued) tON td(ON) tr VDS + tOFF td(OFF) tf 90% VGS RL 90% DUT RGS VGS - VDD 0 10% 90% 10% VGS 0 10% 50% PULSE WIDTH 50% FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS VDS RL VDD VDS VGS = 10V VGS + Qg(TOT) Qg(5) VDD VGS VGS = 1V 0 Qg(TH) IG(REF) 0 VGS = 5V DUT IG(REF) FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS Soldering Precautions The soldering process creates a considerable thermal stress on any semiconductor component. The melting temperature of solder is higher than the maximum rated temperature of the device. The amount of time the device is heated to a high temperature should be minimized to assure device reliability. Therefore, the following precautions should always be observed in order to minimize the thermal stress to which the devices are subjected. 1. Always preheat the device. 2. The delta temperature between the preheat and soldering should always be less than 100oC. Failure to preheat the device can result in excessive thermal stress which can damage the device. 3. The maximum temperature gradient should be less than 5oC per second when changing from preheating to soldering. 4. The peak temperature in the soldering process should be at least 30 oC higher than the melting point of the solder chosen. 5. The maximum soldering temperature and time must not exceed 260oC for 10 seconds on the leads and case of the device. 6. After soldering is complete, the device should be allowed to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result in latent failure due to mechanical stress. 7. During cooling, mechanical stress or shock should be avoided. (c)2002 Fairchild Semiconductor Corporation RF1K49211 Rev. B RF1K49211 PSPICE Electrical Model SUBCKT RF1K49211 2 1 3 ;rev 6/26/96 DPLCAP CA 12 8 2.11e-9 CB 15 14 2.99e-9 CIN 6 8 1.30e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 15.81 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.04e-9 LSOURCE 3 7 2.37e-10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD S1A RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 3.50e-3 RGATE 9 20 1.57 RLDRAIN 2 5 10 RLGATE 1 9 10.4 RLSOURCE 3 7 2.37 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 11.42e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 14 IT 15 17 GATE 1 RLGATE CIN 10 RSLC1 51 ESLC 50 EBREAK MWEAK MMED MSTRO LSOURCE 8 RSOURCE RLSOURCE RBREAK 18 RVTEMP 19 7 SOURCE 3 RLDRAIN DBREAK 11 + 17 18 DBODY 5 LDRAIN DRAIN 2 RSLC2 5 51 ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6 - - VBAT 22 19 DC 1 ESLC 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*170),3))} .MODEL DBODYMOD D (IS = 1.36e-12 RS = 1.65e-2 TRS1 = 3.88e-3 TRS2 = -5.45e-6 CJO = 2.95e-9 TT = 2.70e-8 M = 0.43) .MODEL DBREAKMOD D (RS = 2.75e- 3TRS1 = -5.01e- 4TRS2 = -1.60e-4) .MODEL DPLCAPMOD D (CJO = 2.40e-9 IS = 1e-30 N = 10 M = 0.55) .MODEL MMEDMOD NMOS (VTO = 1.6 2KP = 1.5 IS = 1e-3 0N = 1 0TOX = 1L = 1 uW = 1u RG = 1.57) .MODEL MSTROMOD NMOS (VTO = 2.0 8KP = 98.0 IS = 1e-3 0N = 1 0TOX = 1L = 1 uW = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.40 2KP = 0.06 7IS = 1e-3 0N = 1 0TOX = 1L = 1 uW = 1u RG = 15.7 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 8.51e- 4TC2 = 7.88e-7) .MODEL RDRAINMOD RES (TC1 = 1.55e- 2TC2 = 5.78e-5) .MODEL RSLCMOD RES (TC1 =1.02e-4 TC2 = 1.07e-6) .MODEL RSOURCEMOD RES (TC1 = 0TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -2.20e- 3TC2 = -7.29e-6) .MODEL RVTEMPMOD RES (TC1 = -5.10e- 4TC2 = 8.07e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.1 VOFF = -1.1) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.1 VOFF = -4.1) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF = 2.5) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.5 VOFF = -0.5) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991. (c)2002 Fairchild Semiconductor Corporation + - RDRAIN 21 16 - VBAT + 8 22 RVTHRES RF1K49211 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM DISCLAIMER FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R) SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R) VCXTM STAR*POWER is used under license FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4 |
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